Equalization inside a serializer/deserializer (SerDes) refers to the correction of inter-symbol interference of the channel. Decision feedback equalization is a common and preferred scheme of equalization inside the serializer/deserializer receivers because it avoids noise and crosstalk enhancement commonly associated with analog equalizers. Decision feedback equalization involves the subtraction of the inter-symbol interference associated with the previous decision from input signal before slicing to get the new decision or bit. Consequently, decision feedback equalization involves feedback with a critical path delay of one unit interval. As the data rates increase and unit intervals decrease, implementing decision feedback equalization becomes challenging. Unrolled decision feedback equalization, in which all the possible outputs are pre-calculated and then the final decision is multiplexed based on the previous bit, also involves a one unit interval critical path for the output multiplexer which still imposes significant challenges at higher data rates. As the data rates approach and exceed 56 Gbps, implementation of a one unit interval multiplexer becomes impractical. Even when practical, the realization of one unit interval multiplexer undesirable due to power consumption.
Consequently, it would be advantageous if an apparatus existed that is suitable for a decision feedback equalization apparatus that spreads out the one unit interval decision feedback equalization multiplexing operation over multiple unit intervals.